1. Field of the Invention
The present invention provides an address decoding method and related memory apparatus by comparing mutually exclusive bit-patterns of addresses.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a functional block diagram of a prior art computer 10. The computer 10 is a microprocessor system, comprising a CPU 12, a chipset 14, a memory apparatus 16, a display card 18, a monitor 20, a peripheral device 22 and a basic input and output system (BIOS) 24.
The memory apparatus 16 usually consists of a few memory modules. For example, there are four memory modules 30A to 30D shown in FIG. 1. Each memory module 30A to 30D comprises a plurality of memory units 34. Each memory unit 34 is used for recording one bit of digital data. The total amount of size of memory apparatus 16 is the sum of the memory size of each memory unit 34 in the memory module 30A to 30D. In the prior art, the memory module is implemented as an independent circuit that can be connected to the computer 10 through the slot so as to compose the memory apparatus 16. The memory size of each memory module can be different. The user can equip his/her own computer with memory modules of different memory sizes as needed. General speaking, the memory units of the memory modules will be located in two rank memory arrays. For example, as shown in FIG. 1, there are two rank memory arrays 32A and 32B in the memory module 30A. The control circuit 28 will control data access to a rank memory array using a control signal. As shown in FIG. 1, the control signals CSp0 and CSp1 are associated with the two rank memory arrays 32A and 32B respectively in the memory module 30A, and the control signals CSp2 to CSp7 are associated with the rank memory arrays in the memory module 30B, 30C and 30D.
As for the address assignment of memory units in the memory apparatus 16, please refer to FIG. 2 (and also FIG. 1). FIG. 2 is a diagram showing the address assignment of each memory unit in the prior art. As shown in FIG. 2, given that the memory modules 30A to 30D respectively have 2^25, 2^27, 2^28 and 2^26 memory units, the memory size of the modules 30A to 30D is 32 MB, 128 MB, 256 MB and 64 MB respectively. When the computer reboots, the control circuit 28 will assign the addresses previously increased incrementally to each memory unit in the memory modules 30A to 30D. Certainly the associated address of each memory unit is represented as a binary address. For example, as shown in FIG. 2, the associated address of each memory unit is represented as a 32-bit binary number, starting from Bit 0 as the least significant bit (LSB) and ending with Bit 31 as the most significant bit (MSB). After assigning the address, the first memory unit of the memory module 30A will be assigned the address 36A, a binary number of “000 . . . 0” (all ‘0’s). The following associated address of each memory unit will increase by degrees in sequence. Take the second and third memory unit as an example, the address of the second unit is 36B, a binary number of “00 . . . 01” (only Bit 0 is ‘1’) while the address of the third unit is 36C, an incrementally increased value “0 . . . 010” (only Bit 1 is ‘1’). When it comes to the second unit from the end, the associated address has been increased to “0 . . . 01 . . . 10” (Bit 1 to Bit 24 are ‘1’ and the rest are ‘0’); and for the last memory unit (that is, the 2^25th memory unit), the associated address 36E, has been increased one from the address 36D to “0 . . . 01 . . . 1” (Bit 0 to Bit 24 are ‘1’ and the rest are ‘0’).
When the control circuit 28 is performing the address assignment, the apparatus 16 will view all the memory units in the memory modules as a whole. Therefore, when the control circuit 28 is assigning addresses to units in the memory module 30B, the value of the address will continuously be increased incrementally from the address 36E, which is the largest address in the memory module 30A. As shown in FIG. 2, the first memory unit of the memory module 30B will be assigned the address 38A; the value of the address 36E will be increased by one to “0 . . . 010 . . . 0” (only Bit 25 is ‘1’), which represents the (2^25+1)th memory unit of the memory apparatus 16—that is, the (2^25+1)th memory unit counting from the first memory unit of the memory module 30A (the memory unit associated with the address 36A). Similarly, the second memory unit in the memory module 30B will be viewed as the (2^25+2)th memory unit in the memory apparatus 16, and its associated address 38B will be increased by one from address 38A to a binary number of “0 . . . 010 . . . 01.” (Only Bit 0 and Bit 25 are ‘1’.) Since there are 2^27 memory units in the memory module 30B, the last two memory units in the memory module 30B will become the (2^25+2^27−1)th and the (2^25+2^27)th memory units in the memory apparatus 16, and their associated addresses 38C and 38D will be increased respectively to “0 . . . 01001 . . . 10” (Bit 1 to Bit 24 and Bit 27 are ‘1’, and the rest are ‘0’) and “0 . . . 01001 . . . 11” (Bit 0 to Bit 24 and Bit 27 are ‘1’ and the rest are ‘0’).
By the same token, in the memory module 30C (that is, the third memory module), the associated address 42A of its first memory unit (that is, the smallest address in the memory module 30C) will be increased by one from the value of address 38D to a binary number of “0 . . . 0100 . . . 0” (only Bit 25 and 27 are ‘1’), which also represents the (2^25+2^27+1)th memory unit counting from the memory unit in address 36A. When it comes to the 2^28th address 42B in the memory module 30C (that is, the largest address in the memory module 30C), its value will be increased to a binary number of “0 . . . 011001 . . . 1” (Bit 0 to B24, Bit 27 and Bit 28 are ‘1’ and the rest are ‘0’), which represents the (2^25+2^27+2^28)th address linearly increased from the address 36A. Similarly, in the fourth memory module 30D, the address 44A is associated with the first memory unit to a binary number of “0 . . . 10101 . . . 0” (Bit 25, 27 and 28 are ‘1’) while the address 44B of the last memory unit is increased to “0 . . . 011101 . . . 1” (Bit 26 to 28 and Bit 0 to 24 are ‘1’ and the rest are ‘0’), which represents the (2^25+2^27+2^28+2^26)th address counting from the address 36A.
After assigning the address, the first and the last addresses in each memory module will be assigned an ending address. As shown in FIG. 2, all the addresses are smaller than the first address 38A in the memory module 30B. Therefore, the address 38A can be viewed as the ending address 46A associated with the memory module 30A. Similarly, in the memory module 30B (and the memory module 30A), addresses assigned to each memory unit are smaller than the smallest address 42A in the memory module 30C. Therefore, the address 42A can be viewed as the ending address 46B associated with the memory module 30B. On the other hand, all the addresses assigned to the memory module 30C, 30A and 30B are smaller than the ending address 46C (that is, the smallest address 44A in the memory module 30D) associated with the memory module 30C. Finally, all the addresses in the memory module 30D are smaller than the ending address 46D. Please note that the ending address 46A to 46D are the result of the unit address increment in each memory module. Given that the ending address 46A shows a binary number of 2^25, that number also represents the memory size of the memory module 30A (the amount of memory units in the memory module 30A); the ending address 46B is represented as a binary number of (2^25+2^27), which is the total amount of the memory size of the memory module 30A and 30B; the ending address 46C is represented as a binary number of (2^25+2^27+2^28), that is the total amount of the memory size of the memory module 30A, 30B and 30C. Finally the ending address 46D is represented as (2^25+2^27+2^28+2^26), which is also the total amount of the memory size of the memory module 30A to 30D.
Please refer to FIG. 3 (also FIG. 1 and FIG. 2). FIG. 3 is a functional block diagram, which shows how the control circuit 28 performs initial address decoding. In the control circuit 28, there is an access module 51, a plurality of subtraction modules 48A to 48D, and a logic module 50. The access module 51 is used for caching the given address 54 the CPU (or other circuits) transmitted to the control circuit 28; and the control circuit 28 will perform the initial address decoding. In the prior art, when the control circuit 28 is going to perform initial address decoding for determining in which memory module this given address 54 is located, the control circuit 28 can use software or hardware to implement the subtraction modules 48A to 48D and the logic module 50. The subtraction modules 48A to 48D are used to subtract the given address 54 from the ending addresses 46A to 46D in order to determine which one is smaller, the given address or the ending address 46A to 46D. (Please also refer to FIG. 2.) The logic module 50 will further integrate the result of the subtraction module to determine the memory module in which the given address 54 is located. The associated decoding result will also trigger a series of signals, such as the directive signals HPA to HPD to represent the memory module in which the given address 54 is located.
Given that the address 54 is located in the memory module 30A, the given address 54 will be smaller than each ending address 46A to 46D. Given that the address 54 is located in the memory module 30B, the given address 54 will be smaller than the ending address 46B to 46D but not smaller than the ending address 46A. Similarly, when the memory unit associated with the given address 54 is located in the memory module 30D, the given address 54 is only smaller than the ending address 46D but not smaller than the ending address 46A to 46C. As shown in FIG. 3, if the given address 54 is “0 . . . 010010 . . . 0” (only Bit 25 and 28 are “1”), it is not smaller than the ending address 46A and 46B but smaller than the ending address 46C and 46D. As a result, the logic module 50 can determine the memory unit associated with the given address 54 in the memory module 30C. Furthermore, the logic module can bring up the voltage of the directive signal HPC to a higher state of “1” (or “true” logically) for representing that the given address 54 is located in the memory module 30C; and the voltage of other directive signal HPA, HPB and HPD is at a lower state “0” (or “false” logically) for representing that the given address 54 is not located in the memory modules 30A, 30B and 30D.
However, no matter if the subtraction modules in the prior art in FIG. 3 are implemented as hardware circuits or micro-controller software programs operated by the north bridge circuit 26A, the efficiency of the operation is not great. Take the embodiment of hardware circuit as an example; to implement a subtraction module to subtract one binary number from another, one can first get a complement (such as one's complement or two's complement) for one of these two numbers as the negative value of that number. Then the adder will add the negative value of that number to another number. While adding the two binary numbers together, the adder starts with adding the least significant bit (LSB, Bit 0) of the two numbers together and then adding the next bit of the two numbers together and then the next. The process will not stop until the adder finishes adding the most significant bit of the two numbers together.
As described above, while performing the addition of the two binary numbers, the addition of the bit in one position will not be performed until the carry bit, obtained from the addition of the previous bit of the two numbers, is returned. Therefore, the amount of time needed for the addition of the two binary numbers is the total time needed for adding bits in each position together. That is, the more bits the binary numbers have, the more time is needed for performing the addition. As a result, initial address decoding in the prior art has a clear influence by the characteristic. While the prior art in FIG. 3 compares the given address 54 with each ending address 46A to 46D by performing the operation of subtraction in the subtraction module, a considerable amount of time is consumed on the operation of subtraction, resulting in the low efficiency of initial address decoding. Due to the low efficiency of address decoding, the CPU 12 (see FIG. 1) cannot have rapid and efficient access to memory resources in the memory apparatus 16, and therefore drags down the operating efficiency of the computer 10 as a whole.